An optical disk unit has been used as a memory apparatus in a computer system. The optical disk unit has been required to increase memory capacity as well as to minimize the unit. For this reason, in any optical disk unit, the entire unit has been minimized by reducing circuit components to be packaged on the board or by making smaller an area for each component to be packaged thereon, and general controls have been provided by a single processor.
FIG. 13 is a block diagram showing a memory apparatus based on the conventional technology as a whole, and FIG. 14 is a block diagram showing circuits based on the conventional technology. The diagrams shown in FIG. 13 and FIG. 14 assume a magneto-optic disk unit as an optical disk unit respectively. As shown in FIG. 13, a control circuit for the magneto-optic disk unit has the configuration as described below. Namely, a micro-processor (MPU) 61 provides main controls over the unit. A random access memory (RAM) 65 is a memory used for processing by a MPU 61.
A read-only memory (ROM) 66 is a memory for storing therein a control program executed by the MPU 61. An optical disk controller/optical disk driver (described as ODC/ODD hereinafter) 63 is firmware, provides interface controls for a host computer which is not shown in the figure, and comprises an ODC section for encoding/decoding data and an ODD section for providing drive controls. A random access memory (RAM) 67 is used as a buffer memory for read data/write data operations.
A digital signal processor (DSP) 64 provides servo controls over an optical head of an optical disk drive mechanism. A control logic circuit 62 is a logic circuit group for executing digital signal transaction with the optical head or the like for the optical disk drive mechanism. The control logic circuit 62 prepares a timing gate for data transaction between the processor 61 and optical head. These digital circuits 61, 65, 63, 64 and 66 are connected to each other through a shared address/data bus line 68. An analog circuit is provided in addition to those digital circuits. The analog circuit comprises a read circuit 69, a write circuit 71, a driving circuit 72 or the like.
The read circuit 69 amplifies output from an optical detector 90 for the optical head, and then generates a waveform. This generated pulse is output to the ODC/ODD 63 as read data. The write circuit 71 drives a laser diode 91 of the optical head for emitting pulses therefrom with specified power according to write data. With this operation, data is written in an opticaldisk. The driving circuit 72 drives a driving mechanism 92 for the optical head according to a servo signal from the DSP 64. The driving mechanism 92 for the optical head includes a focus actuator for the optical head, a track actuator therefor, and a motor for moving the optical head or the like. A servo AGC circuit 81 prepares a focus error signal as well as a track error signal from output detected by the optical detector 90 for the optical head, and outputs the signals to the DSP 64.
Next description is made with reference to the block diagram of circuits shown in FIG. 14. As shown in FIG. 14, the MPU 61 and control logic circuit 62 are formed in a single chip. Then, a clock source 73 is connected to this single chip LSI. The RAM 67 and a terminal resistor 74 of the host interface are connected to the ODC/ODD 63. The RAM 65 and ROM 66 are connected to the MPU 61 through the address/data bus line 68.
Provided in an optical head 80 are the write LSI 71 and the preamp/servo AGC circuit 81. The write LSI 71 provides light-emission controls for reading or writing over the laser diode (light-emitting element) 91. The write LSI 71 is connected to the control logic circuit 62 and provides light-emission controls for reading or writing over the laser diode 91 according to instructions from the MPU 61.
The preamp/servo AGC circuit 81 converts a current detected by the optical detector 90 for the optical head 80 to a voltage, and then prepares, a regenerative signal, a focus error signal and a track error signal. The focus error signal and track error signal are output to the DSP 64. The read circuit 69 generates a waveform of a regenerative signal for the preamp/servo AGC circuit 81, and outputs the pulsed read data to the ODC/ODD 63. It should be noted that ananalogs switch 69-1 and a reversing circuit 69-2 are provided in the read circuit 69.
The analog LSI 75 is formed by integrating analog circuits such as an operational amplifier and a comparator used in the unit. The analog LSI 75 executes operations for filterin and amplifying a focus error signal and a track error signal, or the like. An amplifier 76 is an operational amplifier for an analog filter. This amplifier 76 executes an operation for filtering output from the preamp/servo AGC circuit 81. An amplifier 77 is also an operational amplifier for an analog filter, and executes an operation for further filtering output from the analog LSI 75.
Provided in the optical disk drive mechanism 82 is a lens-position detector 93 for detecting a position of a lens for the optical head 80. An AGC amplifier 70 is a circuit for executing current/voltage conversion for a sensor signal from the detector 93. A focus actuator 92-1, a track actuator 92-2 and a voice coil motor 92-3 are provided in the optical disk drive mechanism 82 as a driving mechanism for the optical head 80.
The focus actuator 92-1 drives a lens for the optical head 80 in the focus direction and adjusts a focus position of an optical beam. The track actuator 92-2 drives a lens for the optical head 80 in the transverse direction of a track and finely adjusts a track position of an optical beam. The voice coil motor 92-3 moves the optical head 80 in the direction crossing the track on the optical disk.
The DSP 64 executes processing for servo controls in various modes according to a focus error signal and a track error signal each from the analog LSI 75 as well as to a lens-position detection signal from the AGC amplifier 70. Namely, th DSP 64 provides focus servo controls, track servo controls, and seek controls.
The DSP 64 has a group comprising A/D converters each for converting from analog to digital a focus error signal, a track error signal, and a lens-position detection signal. Then the DSP 64 computes servo control values (focus servo control value, track servo control value, and seek servo control value) according to those digitally converted signals. The DSP 64 also has a group comprising D/A converters each for converting each of the servo control values to an analog servo control volume. The driving circuit 72 for servo as well as seek controls is connected to the DSP 64.
This driving circuit 72 comprises a focus driver circuit 72-1 for driving the focus actuator 92-1 according to a focus servo control volume, a track driver circuit 72-2 for driving the track actuator 92-2 according to a track servo control volume, and a VCM driver circuit 72-3 for driving the voice coil motor 92-3 according to a seek servo control volume.
Further provided in the mechanism 82 are an eject motor 93-1 for ejecting an optical disk cartridge to the outside and a spindle motor 93-2 for rotating an optical disk.
An eject driver circuit 78-1 drives the eject motor 93-1 according to instructions from the MPU 61 via the control logic circuit 62. A spindle driver circuit 78-2 drives the spindle motor 93-2 according to instructions from the MPU 61 via the control logic circuit 62.
A coil 94 for a bias magnetic field for loading a magnetic field to the optical disk is further provided therein. A bias driver circuit 79 drives the coil 94 for a bias magnetic field according to instructions from the MPU 61 via the control logic circuit 62. A bias generates a magnetic field of a positive and a negative polarity when a specified current is flown to the coil 94 for a bias magnetic field in the positive and negative directions.
An amplifier 79-1 is an operational amplifier for detecting a bias driving current. A comparator 79-2 is a component for setting a bias driving current value. A dip switch 175 is a switch for setting an address from the outside. A flip flop 176 is a component for maintaining a set value of the dip switch 75. These dip switch 175 and flip flop 176 are provided for an SCSI interface.
FIG. 15 and FIG. 16 are views each showing packaged circuits based on the conventional technology respectively and FIG. 17 is a view for configuration of the memory apparatus based on the conventional technology. FIG. 15 is a top plan view of the circuit board 86, and FIG. 16 is a bottom view thereof. To package each IC circuit as described above, each IC and LSI are packaged, as shown in FIG. 15, on the top surface of the single unit of circuit board 86 based on the conventional technology.
Also packaged on the bottom surface of the circuit board 86 is, as shown in FIG. 16, rest of the circuits such as an IC, and LSIs 65, 66, 67-2. It should be noted that the reference numerals 84-1 to 84-5 shown in FIG. 15 and FIG. 16 indicate connectors respectively each of which is provided for connection to the optical disk drive mechanism. The reference numeral 85 indicates a connector for interface which comprises a SCSI interface connector.
Areas 87, 88 and 89 within a region indicated by dotted lines on the circuit board 86 shown in FIG. 16 are areas each in which an address/data bus line or the like is wired. There are some components on the board such as the bias coil 94 for optical disk drive mechanisms 80, 82 which is high in height, so that there are some areas having a height not sufficient to package components thereon. In those areas, because the components can not be packaged as described above, the address/data bus lines or the like are provided.
As shown in FIG. 17, the circuit board 86 is fixed on the optical disk drive mechanism 82 with screws or the like. The circuit board 86 is fixed to the optical disk drive mechanism 82 with the bottom surface of the board having a comparatively smaller number of packaged components opposite thereto.
In the conventional technology described above, as a control logic circuit 62 for providing drive controls and an ODC/ODD 63 for executing upper interface with a host computer operate under controls by a single unit of MPU for reduction of a circuit scale, when a command is successively issued from the host computer while the control logic circuit 62 is providing drive controls (during seek operation or the like), an interruption by the command to the MPU 61 is generated and the ODC/ODD 63 starts its operation according to the command.
At that point of time, if the host computer operates more slowly than the magneto-optic disk unit, the processing for controls is returned to the control logic circuit 62 after the ODC/ODD 63 finishes the processing for the command and the driving operation can be continued, but there has been a tendency in recent years that a clock frequency of a host computer is becoming higher, which makes the operational speed of the magneto-optic disk unit be far behind as compared to that of the host computer.
As described above, when the operation of the host computer is faster than that of the magneto-optic disk unit, the next command is issued from the host computer at the very moment when the processing for controls is returned to the control logic circuit 62 after the ODC/ODD 63 finishes the processing for the command, so that the processing for controls shifts back again to the ODC/ODD 63 according to the is sued command. For this reason, there has been the possibility hat the driving operation is abnormally terminated because the processing for drive controls by the control logic circuit 62 is impossible to continue due to successive interruption.
It should be noted that there has been also the possibility that this type of abnormal termination in the driving operation may occur when an optical disk as a medium is loaded or when an operation for writing in the medium is executed via a data buffer.